FIELD OF THE INVENTION
The present invention generally relates to computing units, and more particularly to a computing unit provided in, for example, a digital signal processor (DSP).
Recently, the advance of the semiconductor technology has drastically increased the integration density of semiconductor elements, and facilitated down-sizing of DSPs. This has resulted in reduction in the cost of DSPs.
With the cost reduction of DSPs, the field to which the DSPs can be applied drastically expands. In the past, the DSPs have been mainly applied to communications devices, such as a modem (modulator-demodulator), and an echo canceller. Recently, the DSPs have been applied to servo control for positioning a read head on a hard disk or an optical disk, and control systems such as engine control and suspension control of automobiles.
Most DSPs used in communications systems are used to perform a high-precision filtering operation. For example, the DSP performs a sum-of-products operation in which an adding value of 32 bits is added to a product having a multiplicand of 16 bits and a multiplier of 16 bits.
However, in the applications to the control systems, the DSPs are used to perform not only the high-precision filtering operation but also a low-precision operation. A low-precision operation is, for example, an operation in which the result of the operation consists of 16 bits. Such a low-precision operation is applied to control for peripheral circuits, such as a timer, an analog-to-digital (A/D) converter and a serial interface.
The hardware structure of the existing DSPs is equipped with a high-precision arithmetic and logic unit for the purpose of speedup of the filtering operation. The aforementioned filtering operation (the sum-of-products operation) is carried out during one machine cycle of the DSPs equipped with the high-precision arithmetic and logic unit. Generally, the high-precision arithmetic and logic unit needs a large quantity of hardware, and does not perform the operation at high speed. Hence, it takes a long time to output the operation result. With the above in mind, normally, the machine cycle is selected so that it is slightly greater than the operation speed of the arithmetic and logic unit. The above machine cycle is the limit regarding the processing speed of the DSPs. Further, the large quantity of hardware of the arithmetic and logic unit degrades the yield rate of DSPs, and causes the DSPs to be expensive.
The existing DSPs perform a low-precision operation within one machine cycle. In practice, the low-precision operation is completed within the first half of the machine cycle, and no operation is carried out during the second half of the machine cycle. Hence, the case where the existing DSPs perform both the high-precision operation and the low-precision operation do not fully utilize the high-speed operation capability of the DSPs.
The performance of the DSPs will be improved in the future, and the ratio of the number of non-high-precision operations to high-precision operations for the peripheral circuit control will be increased in the applications of the DSPs to the control systems. Under the above circumstances, it will be considered desirable that DSPs applied to the control systems be equipped with an arithmetic and logic unit which has a small quantity of hardware and a high-speed operation capability.
In the case where an operation is carried out with a precision twice as high as that of the existing DSPs by means of a DSP equipped with the above-mentioned low-precision arithmetic and logic unit, a clip step will be needed in order to clip the operation result to a maximum or minimum value if the operation result overflows. In order to improve the operation speed of the low-precision arithmetic and logic unit, it is necessary to reduce the time necessary for the clipping process.